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AN702 vishay siliconix document number: 70576 www.vishay.com faxback 408-970-5600 1 efficient isdn power converters using the si9100

one of the latest technology revolutions, an integrated worldwide telecommunications network, will be accompanied by another advance in power conversion technology. the integrated services digital network (isdn) will allow different forms of information (voice, computer data, video, facsimile, etc.) to be transmitted over the telephone network. the international consultative committee for telephone and telegraph (ccitt) has proposed standards for the interfaces required to implement isdn. although the standards have yet to be formally adopted, telecommunications companies are moving ahead with pilot test programs, and semiconductor makers are developing chip sets to build isdn hardware. every network terminator (nt), signal regenerator (rg), and terminal equipment (te) unit used for the implementation of isdn will require a power converter. [1] a major requirement of these telecom applications (due to the need for emergency-mode operation from a high-impedance source) is high-efficiency energy conversion at fractional-watt power levels. minimization of parts count, another key factor for the design of these power converters, is sought to simultaneously achieve low cost and high reliability. bic/dmos integrated circuit technology is ideally suited for the power requirements of isdn. the analog and digital logic functions needed for pulse-width modulation can be implemented in cmos to minimize quiescent current to the controller. dmos transistors provide high-voltage power switching with both very low dynamic and gate drive losses. integration of the cmos controller on the dmos power device yields the best overall performance at the lowest cost and component count.
while some differences exist between designs, there are several requirements in addition to efficiency which are common to isdn power converter applications. these include: reliable start-up and operation from the high source impedance of telephone subscriber lines (u-interface only) current limiting to prevent failure of other network terminals when one power converter output is shorted (s-interface only) a free-running internal oscillator for start-up as well as independent operation, which can be synchronized to an external clock signal electromagnetic interference (emi) filtering to limit conducted emissions during both start-up and normal operation, as well as during equipment connections and disconnections. the si9100 power ic facilitates compliance with these design requirements with a minimum number of external parts. to illustrate this capability, a discontinuous conduction mode (dcm) flyback converter was built and tested. measured efficiency was greater than 80% for a wide range of loads, and 60% efficiency was achieved with only a 15-mw load. before describing the circuit concepts in detail, it is instructive to note the main features of the isdn power-feeding concept which has been endorsed by the ccitt.

figure 1 is a block diagram of the isdn basic access configuration. the two-wire transmission line defined at the u-interface provides a 192 k-bits-per-second (bps) digital data path which connects subscriber equipment to the local telephone exchange. although isdn permits many new services to be offered, the basic service of voice transmission remains a vital function. therefore, the network power feeding from batteries in the local telephone exchange remains an essential part of modern telephone system planning. the network terminal (nt) connects the local loop, called the s-bus, to the u-interface at the customer's premises. isdn-compatible terminals (te1) communicate at a standard 64 k-bps rate over the four-wire s-bus. non-isdn-compatible terminal equipment (te2), such as analog phones, must connect to the s-bus via a terminal adapter (ta). to minimize noise-coupling problems, the s-bus must be galvanically isolated from the two-wire u-interface. the ccitt recommendations call for an off-line power converter in the nt to supply 4 w at 40 v nominal to the s-bus during normal operation (for up to four telephones with full features). other terminal equipment (e.g., fax terminals) would be fed solely from local ac power lines. in the event of a power outage, one telephone at the customer premises must be fed from the central office battery. this procedure is accomplished by reversing the voltage polarity on the s-bus. non-priority terminals have a diode input which isolates them during emergency-mode operation. a single telephone terminal is fed via a full diode bridge, allowing it to operate during the emergency. a signal regenerator may be required for long loops (u-interface). the deutsche bundespost (dbp) proposes to increase the feeding voltage from 60 v to 93 v to compensate for voltage drops on long lines requiring signal regeneration. the standard telephone line voltage used in many other parts of the world is 48 v. whatever the voltage, the problem for power converters connected to telephone subscriber lines remains the same--they are fed from a high-impedance source. .com .com .com .com 4 .com u datasheet
AN702 vishay siliconix www.vishay.com faxback 408-970-5600 2 document number: 70576 nt r g s 110/220 vac sbus local telephone exchange transmission line central office switch te1 te1 te2 ta r u u needed only for long loops battery voltage (48 or 60 v typically) customer premises figure 1. isdn basic access configuration 110/220 vac
the impedance of telephone subscriber lines limits the amount of power that can be supplied to the load. referring to figure 2, for a battery voltage, v s , and line resistance, r s , the maximum power to the converter is given by equation 1, since the power limit occurs when source and load impedances are equal. ( 1) p max v 2 1 r e v s 2 2 r e v 2 s 4r e r e is defined as the effective low-frequency input impedance of the power converter. for a flyback converter, with waveforms as shown in figure 3, the calculation of the low-frequency input impedance is straightforward. the coupled inductor is designed to ensure operation in the discontinuous conduction mode (dcm). this operation requires that the core flux be reset to zero during each cycle. the current is zero at turn-on and ramps up at a rate given by di/dt = v 1 /l p . the maximum value of the peak primary current, i pk , is (2) i pk di dt (t on (max) ) v 1 l p t s 2 the 50% maximum duty ratio imposed by the si9100 controller limits the aono time of q1 to one-half of the switching period. the average value of the current waveform in figure 3 is the dc current in the inductor, l1. the current ripple in l1 is small, and the average inductor current, i dc , during start-up is one-fourth the peak current value, as given by (3) i dc i pk 2 (d (max) ) 1 pk 4 +5 v 5 v q1 c1 l1 central office (co) battery subscriber line u-interface input filter flyback converter figure 2. power converter with high source impedance r s r e i dc v s v 1 r load .com .com .com .com .com 4 .com u datasheet
AN702 vishay siliconix document number: 70576 www.vishay.com faxback 408-970-5600 3 d < 0.5 (after start-up) figure 3. primary side current waveforms d max = 0.5 (at start-up) i pk i pk di dt v 1 l p 8i dc fs substituting this result into equation 2 gives r e in terms of the primary inductance, l s , and switching frequency, f s (f s = 1/t s ). (4) r e v 1 i dc 8l p f s l p effectively acts as a current limiter during start-up, thus eliminating the need for active current limiting circuitry. the value of l p must be chosen between a minimum value, which sufficiently limits start-up current, and a maximum value, which permits the rated throughput power to the load. assume, for example, the maximum load condition given in table 1. [2] the input power to the converter is the output power divided by the efficiency. (5) p in p o 0.650 0.80 0.813 w worst-case efficiency at maximum load is assumed to be equal to 80%. the input power to the converter is given by (6) p in 1 2 l p i 2 pk f s as seen from figure 3, if l p is doubled, i pk is reduced by half. therefore, p in varies in inverse proportion to l p . referring again to figure 2, the dc analysis of the input characteristics gives (7) v 1 = v s i dc r s equations 2, 6, and 7 can be combined to give a quadratic equation which yields the maximum and minimum values for l p . a graphical approach, however, gives the same answer and, at the same time, provides more insight into system behavior. after start-up has occurred, the power converter no longer presents a constant impedance at the input terminals. instead, a constant power characteristic pertains, given by (8) p in = (v 1 ) (i dc ) = constant the demonstration flyback converter was designed to operate from a battery voltage of 48 v and a maximum line resistance of 600 . the constant power curve for (v 1 ) (i dc ) = 0.813, with the load line defined by v s = 48 v and r s = 600 , are plotted in figure 4. the intersection of the load line with the constant power curve determines two operating points, a and b, which occur at (v 1 , i dc ) = (14.6 v, 55.7 ma) and (33.4 v, 24.3 ma). if v s is slowly increased from zero, v s and i dc increase along the line, whose slope is r e , from the origin to the constant power curve. this analysis is an oversimplification since a step increase in voltage is more likely to occur at power-up. however, worst-case start-up conditions occur at maximum r s , which guarantees that the input filter is heavily overdamped. therefore, the increase in v 1 is monotonic, and the results of the simplified analysis are valid. the lines from the origin to points a and b define the minimum and maximum values for r e , and with equation 4, also determine the limits for l p . r e(min) = 14.6/0.0557 = 263 r e(max) = 33.4/0.0243 = 1.37 k for a switching frequency design value equal to 20 khz, equation 4 gives l p(min) = 1.64 mh l p(max) = 8.65 mh l p may be chosen near the upper end of the permissible range for maximum start-up current limiting, or it may be chosen for maximum power transfer on a high-resistance line. setting r e = r s = 600 for maximum power transfer gives l p r e 8f s 600 ( 8 )( 20, 000 ) 3.75 mh the latter approach was chosen for the demonstration converter (see schematic in figure 5). the si9100 functional diagram is given in figure 6 for reference. .com .com .com .com .com 4 .com u datasheet
AN702 vishay siliconix www.vishay.com faxback 408-970-5600 4 document number: 70576
operating mode +5-v current 5-v current output power measured efficiency normalactive 100 ma 30 ma 650 mw 87% normalpower down 11 ma 3 ma 70 mw 79% emergencyactive 55 ma 9 ma 320 mw 88% emergencypower dpwn 3 ma 0 ma 15 mw 60% 50 40 30 20 10 0 60 70 80 010 20 304050 60 7080 figure 4. flyback converter operating states a b constant power curve (v 1 . i dc = 0.813) maximum r e , l p minimum r e , l p i dc in ma v 1 in volts gnd (optional) sync input 1000 pf 10 k c9 r7 20 mh 48 v r3 920 k r1 390 k 7 8 1 4 10 9 5 11 12 2 3 6 13 14 nc nc r4 240 k r6 47 k r5 75 k 1n4148 cr1 1n5819 cr3 1n5819 cr2 +5 v 5 v l2 (rm8pa630 -3b7 core) si9100 figure 5. isdn flyback converter c1 20 f 100 v c10 0.1 f 0.022 f c3 c2 0.01 f c8 1 f c5 220 f c4 0.1 f c7 47 mf c6 0.1 f n s 1 n s 2 n s 3 n p r2 2 1 / 2 w n p = 77 turns n s 1 = 18 turns n s 2 = 18 turns n s 3 = 35 turns l1 .com .com .com .com .com 4 .com u datasheet
AN702 vishay siliconix document number: 70576 www.vishay.com faxback 408-970-5600 5 figure 6. si9100 functional diagram + + + + + fb comp discharge osc 14 (20) 13 (18) 9 (12) 8 (11) 7 (10) 2 v ref gen r s q r s q drain source 3 (5) 5 (8) 4 (7) 11 (16) 12 (17) current-mode comparator c/l 1.2 v undervoltage comparator reset 8.1 v 8.6 v bias current sources to internal circuits 10 (14) 1 (2) 6 (9) 2 (3) comparator error amplifier v ref v cc +v in v cc shutdown 4 v (1%) osc out osc in note: figures in parenthesis represent pin numbers for 20-pin package. v in (body) clock ( 1 / 2 f osc )

measured efficiency data for the flyback converter is given in the last column of table 1. most notable is the 60% efficiency at a load of only 15 mw, which is allowed by the low quiescent current requirement of the cmos control circuitry in the si9100. although power converters can operate at much higher frequencies, the dynamic losses incurred reduce the efficiency during the power-down state. the switching speed (30-ns typical) of the dmos output transistor in the si9100 permits operation above audible frequencies with very low dynamic and drive losses. such performance cannot be achieved with bipolar transistors. a single resistor, r3, sets the oscillator frequency at approximately 34 khz. a positive sync pulse (5-v amplitude and 0.5- s pulse width) at 40 khz was fed through r7 and c9 to pin 8 to demonstrate the principle of synchronization with an external clock. typically, the free-running frequency should be set at 10 to 20% below the external clock frequency (note that the switching frequency is of the oscillator frequency). start-up characteristics were verified by connecting a 600- resistance from a dc power supply to the converter input terminals. reliable start-up was demonstrated at maximum load for supply voltages as low as 44 v. with zero source resistance inserted in the line, the converter maintained regulation down to an input voltage of 23 v. in both cases, the maximum operating voltage is 70 v for the si9100 . the inductor, l1, was wound with 540 turns of #32 magnet wire on a #55206 molypermalloy powder core. the relatively high series resistance of this inductor (6 ) provides series damping of the input filter. this damping reduces peaking of the filter output impedance, preventing degradation of the control loop response at the filter resonant frequency when the supply is operated from a low-resistance source. measured ripple on both outputs was less than 50 mv peak to peak, and regulation was better than 5% over line and load. the 5-v output increases from 5.05 v to 5.75 v when totally unloaded. the current-mode controller of the si9100 provides fast current-limiting response in the event of a shorted output. with either output shorted to ground, the measured value of short-circuit current drawn at the converter input was 30 ma. any output terminal can be shorted for an indefinite period with no resulting high stress condition on the si9100. normal operation resumes when the short circuit is removed. .com .com .com .com .com 4 .com u datasheet
AN702 vishay siliconix www.vishay.com faxback 408-970-5600 6 document number: 70576 the input filtering provided by l1 and c1 provides a calculated attenuation of 68 db at the fundamental of the switching frequency. this allows compliance with fcc class b and vde-0871/b requirements; however, conformance testing to these specifications was not performed. common-mode noise coupling is minimized by the si9100 since the mosfet drain is electrically isolated from the package case (a 14-pin dip). therefore, very little parasitic capacitance exists from drain to ground. since the si9100 places both the driver and mosfet on the same chip, gate driver lead lengths are reduced from a few centimeters for discrete designs to a few hundred microns. the 5-ma/ s dynamic current limit required during connection of equipment to the s-bus [3] is met by selecting a suitably high value, 20 mh, for l1. since several ohms of series resistance is desired, a small wire gauge is used and the inductor is not prohibitively large. a smaller value may be chosen for l1 where the emi requirements are less critical.
bic/dmos power ic technology is ideally suited for the requirements of low-power dc/dc converters, such as those required for the implementation of isdn. a circuit design for an 85%-efficient power converter using the si9100 smartpower ic has been presented here. measured performance data is given, along with a graphical analysis method for ensuring reliable start-up when power is fed from a high-impedance source. 1. rosenbaum, d. and k.h. stolp. athe feeding conception of the isdn basic access,o ieee intelec conference proceedings, munich, frg, oct.14-17, 1985, 505-512. 2. sigloch, r. arequirements for small high efficiency dc/dc converters in complex communication networks,o ieee intelec conference proceedings, toronto, canada, oct 19-22, 1986, 197-202. 3. krautkramer, w. and b. schickling. aremote power feeding of isdn-terminals at the basic access,o ieee intelec conference proceedings, munich, frg, oct. 14-17, 1985, 513-519. .com .com .com .com 4 .com u datasheet

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